In semiconductor industry, the conductive areas in a semiconductor material are generally formed of impurity-doped regions, such as source and drain regions of a metal-oxide semiconductor (MOS) transistor. The conductivity of such an impurity-doped region depends on the concentration of the impurities therein. The higher the concentration of the impurities is, the higher the conductivity of the doped region achieves.
In general, there are various devices, including N-type MOS (NMOS) transistors, P-type MOS (PMOS) transistors, and complementary MOS (CMOS) transistors, built on a semiconductor wafer. Different types of doped regions are formed in these devices with different carriers, wherein electrons are provided as carriers by N-type impurity dopants, and electric holes are provided as carriers by P-type impurity dopants. Specific contact regions in specific devices must be electrically interconnected so as to implement the whole desired circuit function. Normally, these contact regions are already doped conductive regions and serve as electrodes in those devices. However, when the integration of the wafer increases and the dimension of the device scales down, the original doped concentration for the devices' electrodes may no longer provide a sufficient conductivity for the contact regions. Therefore, a contact ion implantation must be carried out to increase the doped concentration of the contact regions.
FIG. 1 illustrates an example of a semiconductor wafer 2 that consists of various devices with doped regions of different conductive types. A twin-well CMOS device is shown with an N-well region 4, a P-well region 6, field oxide regions 8, a PMOS device 10, and an NMOS device 20. A dielectric layer 30, wherein contact holes 32 and 34 are opened to provide contact to the interconnecting lines, is formed on the wafer. Generally, contact holes 32 and 34 are formed aligned to the source and drain regions 14 and 24 of the transistors, which are already doped conductive regions. As mentioned above, the original doped concentration for the source and drain regions can no longer provide a sufficient contact conductivity. Therefore, a contact ion implantation must be carried out to form contact regions for the source and drain regions.
In a conventional manner as mentioned above, masks with different patterns are usually used in different types of ion implantation. FIG. 2 illustrates the two mask patterns adopted for the example shown in FIG. 1. For the contact ion implantation of P-type ions, an implantation mask 40 as shown in FIG. 2A are patterned on the wafer. The blanket P-type ion implantation and the mask removing are then performed in sequence to form the P-type contact regions 16 in the PMOS device. Thereafter, an implantation mask 42 as shown in FIG. 2B are patterned on the wafer. The blanket N-type ion implantation and the mask removing are subsequently performed to form the N-type contact regions 26 in the NMOS device. In this method, two mask patterning, and two masking removing must be carried out. The fabrication processes are complicate.